[LLVMdev] Declare multiple data type for a register class in tblegen

[Xiaochu Liu]

Hi everyone,

I tried to declare multiple data type [i64, i32, v2i32] for a 64 bit
register class GPR. It works OK but I have one problem that is hard to find.

When I tried to map a load instruction of a v2i32 type (LOAD v2i32:$dst) to
load GPR, it always generate two LOAD i32 instead of one LOAD v2i32. Any
folds understand how this works?

Xiaochu
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