[LLVMdev] Encoding instructions with inconsistent formats

[Dylan McKay]

I can't get it to work with pattern matching. My operand is defined like so:

def LDSTPtrReg : Operand<i16>
{
    let MIOperandInfo = (ops PTRREGS);
    let EncoderMethod = "encodeLDSTPtrReg";
}

I am able to use it in the place of PTRREGS in the definition of the LD
instruction, but if I use it in an instruction matching pattern,
compilation fails with the error "Unknown leaf kind:
LDSTPtrReg:i16:$ptrreg".


On Sun, Feb 1, 2015 at 10:26 AM, Dylan McKay <dylanmckay34 at gmail.com> wrote:

> You could probably create a new
>> Operand subclass with a custom EncoderMethod that gets assigned to
>> both the dddd and the odd field
>
> Ah, I hadn't realised that the encoder method had access to the containing
> instruction.
>
> I believe your method will work well, thanks!
>
> On Sun, Feb 1, 2015 at 7:10 AM, Tim Northover <t.p.northover at gmail.com>
> wrote:
>
>> Hi Dylan,
>>
>> One way to view those instructions is that the extra bit is actually
>> part of how the register is encoded. You could probably create a new
>> Operand subclass with a custom EncoderMethod that gets assigned to
>> both the dddd and the odd field.
>>
>> Something like:
>>
>> def BasicMemXYZ : Operand<i16> {
>>   let MIOperandInfo = (ops XYZReg); // Sorry, don't know what you've
>> called it
>>   let CustomEncoder = "encodeXYZForBasicMem";
>> }
>>
>> Associate that operand with 5 bits in the instruction instead of 4 and
>> let the C++ set the final bit as appropriate.
>>
>> Cheers.
>>
>> Tim.
>>
>
>
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