[LLVMdev] Encoding instructions with inconsistent formats

[Tim Northover]

Hi Dylan,

One way to view those instructions is that the extra bit is actually
part of how the register is encoded. You could probably create a new
Operand subclass with a custom EncoderMethod that gets assigned to
both the dddd and the odd field.

Something like:

def BasicMemXYZ : Operand<i16> {
  let MIOperandInfo = (ops XYZReg); // Sorry, don't know what you've called it
  let CustomEncoder = "encodeXYZForBasicMem";
}

Associate that operand with 5 bits in the instruction instead of 4 and
let the C++ set the final bit as appropriate.

Cheers.

Tim.