[LLVMdev] type legalization/operation action

[Tom Stellard]

Adding back llvmdev.

On Tue, Feb 17, 2015 at 09:34:31AM -0500, Tom Stellard wrote:
> On Mon, Feb 16, 2015 at 02:32:36PM -0500, kewuzhang wrote:
> > 
> > Hi Tom, 
> > 
> > Talking about promoting operations.
> > 
> > for i16 type ADD, I promoted it in the tablegen by creating a pattern
> > “
> > def: Pat< (i16  (add i16:$src1 i16:$src2)),  ( IADDs   i16:$src1  i16:$src2)>
> > “ 
> 
> What you've done isn't considered 'promotion'.  This pattern tells the
> instruction selector to *select* i16 add to the IADDs instruction.
> 
> > seems my backend did not complain.
> > and my IADDs is defined as a i32 + i32. I also have the i16 defined, which is same as i32 register
> 
> If the register class you use for IADDs is defined with both i32 and i16
> types (which appears to be the case based on your description), then
> it is expected that the above pattern will work.
> > 
> > my questions are: (1) does  i16 is automatically promoted? or just lucky?
> > (2) I think I should make the pattern to something like:
> > “
> > def: Pat< (i16  (add i16:$src1 i16:$src2)),  ( ConvertToi16 ( IADDs   (ZERO_EXTENDx  i16:$src1)  (ZERO_EXTENDx  i16:$src2)))>
> > “
> 
> This pattern is emulating 16-bit addition using a 32-bit add.
> If you have native 16-bit instructions then you shouldn't use this
> pattern.
> 
> -Tom
> 
> > because the return value is i16 too.
> > Is it necessary?
> >  
> > 
> > best
> > 
> > kevin
> > 
> > > 
> > > Promoting ISD::ADD is not supported.  Take a look in SelectionDAGLegalize::PromoteNode()
> > > to see which opcodes can be promoted.  You will either need to custome lower it or
> > > properly handle it in the PromoteNode() function.
> > 
> 
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