[LLVMdev] type legalization/operation action
kewuzhang
kewu.zhang at amd.com
Thu Feb 5 15:09:16 PST 2015
On Feb 5, 2015, at 5:41 PM, Tom Stellard <tom at stellard.net> wrote:
> On Thu, Feb 05, 2015 at 04:56:25PM -0500, kewuzhang wrote:
>> Dear there,
>>
>> I have a target which is supporting the 32 bit operations natively. Right now,I want to make it support the 16 bits operations as well.
>
> If you want to make 16-bit types legal you need to call:
>
> addRegisterClass(MVT::i16, SomeRegisterClass) in your Target's TargetLowering
> implementation.
>
yeah., it is working.
>> My initial thought is:
>> (1)
>> I can adding something like “ CCIfType< [i16], CCPromoteToType<i32>>”, to the CallingConv.td, then “all” the 16 bits operands will be automatically promoted to 32 bits, it will be all set.
>> but looks it is not the case.
——————how to understand the “promote” in CallingConv.td?
>>
>> (2)
>> Then I tried adding something like “ setOperationAction(ISD::ADD, MVT::i16, Promote)” to the IselLowering, it still failed to select the (i16 + i16)..
>>
>
> Promoting ISD::ADD is not supported. Take a look in SelectionDAGLegalize::PromoteNode()
> to see which opcodes can be promoted. You will either need to custome lower it or
> properly handle it in the PromoteNode() function.
thank you very much!
Think I run into this problem as well, it made me think the Promote is not working.
best
> -Tom
>
>> wondering which part I missed?
>>
>> best
>>
>> Kevin
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