[LLVMdev] Virtual register def doesn't dominate all uses

[Boris Boesler]

Hi Tim,

Am 05.11.2014 um 16:32 schrieb Tim Northover <t.p.northover at gmail.com>:

> Hi Boris,
> 
> On 5 November 2014 07:14, Boris Boesler <baembel at gmx.de> wrote:
>> Hm, these are no patterns like "def : Pat<..>;". These are patterns inside instructions,
> 
> Yep, just give empty square brackets as the pattern for MV
> instructions.

 With the original order of instructions and a MV reg -> reg instruction with an empty pattern, works as you described.

Thanks,
Boris