[LLVMdev] Proposal: "load linked" and "store conditional" atomic instructions

[Tim Northover]

Hi Amara,

I've had a chat with Chandler on IRC since sending this, and it looks
like it's at the very least a less pressing issue.

The summary was that we may want LL/SC instructions in future
(possibly to represent situations currently handed by cmpxchg loops),
but they wouldn't actually solve my problem anyway becaue cmpxchg
would still be the canonical representation when on its own.

Fortunately, he also suggested a very neat solution which deals with
my issues: just run EarlyCSE to tidy up my mess.

On 29 May 2014 13:35, Amara Emerson <amara.emerson at gmail.com> wrote:
> From my admittedly weak understanding, LICM shouldn't hoist loads
> unless they're unordered and this would also apply here to the new
> load linked instruction. In what other cases could the LL/SC become
> separated enough for OS context switches to become a problem?

I think the most likely would be instrumentation passes. They could
even insert another atomicrmw, which would be guaranteed to cause
failure regardless of time taken.

Cheers.

Tim.