[LLVMdev] Proposal: "load linked" and "store conditional" atomic instructions

[Amara Emerson]

Hi Tim,

> 1. Can invalid transformations be done on them? Separating an LL from its
>    corresponding SC by too much almost guarantees failure (an OS task switch
>    happens, clearing the monitor).
>From my admittedly weak understanding, LICM shouldn't hoist loads
unless they're unordered and this would also apply here to the new
load linked instruction. In what other cases could the LL/SC become
separated enough for OS context switches to become a problem?

Amara