[LLVMdev] Legalizing v32i1, v64i1 for Haswell pext/pdep instructions

[Rob Cameron]

Hi, Nadav.

We are expecting to do a lot with bit vector manipulation
at the IR level and then to target multiple back ends.

For example, one of our core operations is the Parabix
Transform - this can be implemented using bit shuffling
among other operations.
http://parabix.costar.sfu.ca/wiki/ParabixTransform

We're also trying to move away from the use of intrinsics
in our libraries and target LLVM IR instead.   If we can
add capabilities to LLVM that give us the performance we
currently achieve with intrinsics-based libraries, we will
be happy. 

This is part of an ongoing research effort; we realize
that we have much to learn and work to do.



----- Original Message -----
> Hi Rob,
> 
> > 
> > One interesting issue that has come up for us is
> > code generation support for the Haswell new instructions
> > pext and pdep.   These instructions shuffle bits within
> > a 64-bit word, either gathering all selected bits to
> > the beginning (pext) or scattering some initial bits
> > throughout (pdep).
> > 
> > A natural model for this is to use shufflevector
> > on v32i1 and v64i1 vectors.   We've got some preliminary
> > notes here:
> > http://parabix.costar.sfu.ca/wiki/BitShuffle
> 
> I agree that one way to model these instructions is as shuffles but
> like you mentioned in your email I expect that implementing this
> would be non trivial. Are you expecting the pext/pdep instructions
> to interact with other instructions? If not, then going with
> intrinsics is probably the best option.
> 
> Thanks,
> Nadav
>