[LLVMdev] Legalizing v32i1, v64i1 for Haswell pext/pdep instructions

[Nadav Rotem]

Hi Rob, 

> 
> One interesting issue that has come up for us is
> code generation support for the Haswell new instructions
> pext and pdep.   These instructions shuffle bits within
> a 64-bit word, either gathering all selected bits to
> the beginning (pext) or scattering some initial bits
> throughout (pdep).
> 
> A natural model for this is to use shufflevector
> on v32i1 and v64i1 vectors.   We've got some preliminary
> notes here:
> http://parabix.costar.sfu.ca/wiki/BitShuffle

I agree that one way to model these instructions is as shuffles but like you mentioned in your email I expect that implementing this would be non trivial. Are you expecting the pext/pdep instructions to interact with other instructions? If not, then going with intrinsics is probably the best option. 

Thanks,
Nadav