[LLVMdev] Be Careful with Positionally-Encoded Operands (AArch64, Mips, AMDGPU, etc.)

[Hal Finkel]

----- Original Message -----
> From: "Tim Northover" <t.p.northover at gmail.com>
> To: "Hal Finkel" <hfinkel at anl.gov>
> Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>
> Sent: Thursday, March 13, 2014 4:06:49 AM
> Subject: Re: [LLVMdev] Be Careful with Positionally-Encoded Operands (AArch64, Mips, AMDGPU, etc.)
> 
> Hi Hal,
> 
> This sounds like a really good idea in general, but...
> 
> >  let noNamedPositionallyEncodedOperands = 1;
> 
> The diagnostics produced are pretty atrocious (an assertion failure
> without even mentioning which instruction is the problem). I couldn't
> in good conscience recommend anyone try it in its present state if
> there are more than 1-2 problems.

Good point. I can add a better diagnostic for this case (where enabling noNamedPositionallyEncodedOperands causes the position-based mapping to run off the end of the operand list); I may not have time until Tuesday, however.

> 
> > I'd like those maintaining the current backends (especially
> > AArch64,
> > Mips, AMDGPU, which I know to be problematic in this regard) to try
> > setting this and: a) fix those definitions that are problematic or
> > b) explain
> > to me that the current behavior is useful.
> 
> I've looked into the SMULH/UMULH case (which appears to be the only
> issue in AArch64). It wasn't intended, but was also harmless.
> Fortunately it can be removed fairly easily so I've done that and
> enabled the flag in r203772.

Thanks!

 -Hal

> 
> Cheers.
> 
> Tim.
> 

-- 
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory