[LLVMdev] codeGen, instruction write one value to the input register.

[kewuzhang]

Tks  Cameron, 

I did some study on it.

Now I am having the same problem as mentioned in this thread;"http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-January/057654.html” ,
> Looking at the X86 back-end code, it looks like there do exist
> multi-output instructions, but they all use physical (implicit) registers
> for the second destination, not arbitrary register types.  And if I change
> the second destination to be a certain physical register, this problem goes
> away in my code.  Is this just not a supported case currently?  Or am I
> doing something wrong?

Wondering if there is any update about it?

best

kevin
On Jun 16, 2014, at 5:08 PM, Cameron McInally <cameron.mcinally at nyu.edu> wrote:

> On Mon, Jun 16, 2014 at 4:51 PM, kewuzhang <kewu.zhang at amd.com> wrote:
>> Hi Guys,
>> 
>> In  LLVM codegen,
>> a typical binary operation instruction is defined something like below:
>> 
>> "  def _rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b),
>>          "xor.pred \t$dst, $a, $b;",
>>      [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>;
>> “
>> 
>> which takes two inputs and write the result to the $dst register.
>> 
>> Then how to define a binary instruction which returns two results, one is
>> written to the $dst register, and the other one is written to one of the
>> inputs? I mean, to implement something like:
>> ”
>> Type sincos( Type input,  Type * cosVal)
>> “
>> 
>> the instruction will compute sin and cos value of input, return the sin
>> result and write the cos result to cosVal.
>> Is there anything special constraints or something I should put onto the cos
>> register?
>> 
> 
> Hey Kevin,
> 
> You might get a good start looking at the AVX2 VGATHER patterns in
> llvm/lib/Target/X86/X86InstrSSE.td. Those patterns return two results.
> They also make use of the @earlyclobber constraint.
> 
> Hope that helps,
> Cameron

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