<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Tks Cameron, <div><br></div><div>I did some study on it.</div><div><br></div><div>Now I am having the same problem as mentioned in this thread;"<a href="http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-January/057654.html">http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-January/057654.html</a>” ,</div><div><pre style="white-space: pre-wrap;">><i> Looking at the X86 back-end code, it looks like there do exist
</i>><i> multi-output instructions, but they all use physical (implicit) registers
</i>><i> for the second destination, not arbitrary register types. And if I change
</i>><i> the second destination to be a certain physical register, this problem goes
</i>><i> away in my code. Is this just not a supported case currently? Or am I
</i>><i> doing something wrong?</i></pre><div><br></div></div><div>Wondering if there is any update about it?</div><div><br></div><div>best</div><div><br></div><div>kevin</div><div><div><div>On Jun 16, 2014, at 5:08 PM, Cameron McInally <<a href="mailto:cameron.mcinally@nyu.edu">cameron.mcinally@nyu.edu</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">On Mon, Jun 16, 2014 at 4:51 PM, kewuzhang <<a href="mailto:kewu.zhang@amd.com">kewu.zhang@amd.com</a>> wrote:<br><blockquote type="cite">Hi Guys,<br><br>In LLVM codegen,<br>a typical binary operation instruction is defined something like below:<br><br>" def _rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b),<br> "xor.pred \t$dst, $a, $b;",<br> [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>;<br>“<br><br>which takes two inputs and write the result to the $dst register.<br><br>Then how to define a binary instruction which returns two results, one is<br>written to the $dst register, and the other one is written to one of the<br>inputs? I mean, to implement something like:<br>”<br>Type sincos( Type input, Type * cosVal)<br>“<br><br>the instruction will compute sin and cos value of input, return the sin<br>result and write the cos result to cosVal.<br>Is there anything special constraints or something I should put onto the cos<br>register?<br><br></blockquote><br>Hey Kevin,<br><br>You might get a good start looking at the AVX2 VGATHER patterns in<br>llvm/lib/Target/X86/X86InstrSSE.td. Those patterns return two results.<br>They also make use of the @earlyclobber constraint.<br><br>Hope that helps,<br>Cameron</div></blockquote></div><br></div></body></html>