[LLVMdev] Possible error in docs.

[Maciej Piechotka]

On Sat, 2014-01-11 at 13:48 +0000, James Courtier-Dutton wrote:
> http://llvm.org/docs/CodeGenerator.html#machine-code-description-classes
> 
> Section starting:
> 
> Fixed (preassigned) registers
> 
> It talks about converting:
> 
> define i32 @test(i32 %X, i32 %Y) {
>   %Z = udiv i32 %X, %Y
>   ret i32 %Z
> }
> 
> into
> 
> ;; X is in EAX, Y is in ECX
> mov %EAX, %EDX
> sar %EDX, 31
> idiv %ECX
> ret
> 
> BUT, where does the "sar" come from?
> 
> Kind Regards
> 
> James

idiv divides (%EDX:%EAX) by it's argument (%ECX). As the code have only
32-bit argument it needs to be bit extended from %EAX to %EDX:%EAX.

sar is arithmetic shift right so sar %EDX, 31 copy the bit sign to all
bits of register.


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