[LLVMdev] Possible error in docs.

[James Courtier-Dutton]

http://llvm.org/docs/CodeGenerator.html#machine-code-description-classes

Section starting:

Fixed (preassigned) registers

It talks about converting:

define i32 @test(i32 %X, i32 %Y) {
  %Z = udiv i32 %X, %Y
  ret i32 %Z
}

into

;; X is in EAX, Y is in ECX
mov %EAX, %EDX
sar %EDX, 31
idiv %ECX
ret

BUT, where does the "sar" come from?

Kind Regards

James