[LLVMdev] Register coalescer and reg_sequence (virtual super-regs)

[Joe Matarazzo]

Was it the subreg lane masks / mapping that was added to address the missed
coalescing?  This solution is nice, but I don't think it'll work for me. I
have 8-element vector registers that can be grouped into virtual super regs
for bulk save/restore, and as soon as I have more than 4 in a tuple, the
unsigned int used to hold the lane masks overflows and switches over to the
"bit 31 set == lanes unresolvable" mode, and coalescing fails.

What about moving the lane masks to a BitVector, that wouldn't need to be
constrained artificially? Too much of a performance impact going that way?

I'd be open to any thoughts/suggestions. I studied the ARM
s_sub/d_sub/q_sub structure but that fits within the 32 bit lane mask. I
also thought that LDM/STM would be similar, but the registers are
physically enumerated, which is different from these virtual super reg
frames I'm trying to construct.


Thanks,
Joe



On Fri, May 31, 2013 at 5:00 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:

>
> On May 31, 2013, at 4:59 PM, Joe Matarazzo <joe.matarazzo at gmail.com>
> wrote:
>
> > I think the last time I pulled from trunk was probably end of last year.
> Some time ago. Does your reply intimate it's fixed on trunk?
>
> Yes, it’s been fixed recently.
>
> /jakob
>
>
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