[LLVMdev] Sub-Register Allocation

[Andrew Trick]

On Jan 11, 2013, at 6:39 PM, Kenneth Waters <kwwaters at gmail.com> wrote:

> 
> LLVM's register coalescer and allocator don't try to reschedule instructions, which seems to be required here.
> 
> I think you're right.  Looking at the instruction schedules before register allocation, shows that it's scheduling the load before the zero move in one case but not the other.
> 
> Is there an easy way I can trick the scheduler into putting these in the right order?  Perhaps by adding a scheduling dependency between the move and the load?

You can try hacking the SelectionDAG scheduler to "AddGlue" between the constant move and load. See ScheduleDAGSDNodes.cpp.

You can also try using an ISEL pseudo instr. I think it's "usesCustomInsert=1".

Maybe someone else has a better idea…

FYI: I've been hoping to add a copy removal feature to the MachineScheduler pass, which is a currently disabled pass. It could cleanup in these situations. However, in this case ISEL should really just emit things in the right order.

-Andy

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