<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><br><div><div>On Jan 11, 2013, at 6:39 PM, Kenneth Waters <<a href="mailto:kwwaters@gmail.com">kwwaters@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div dir="ltr"><br><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="word-wrap:break-word"><div>LLVM's register coalescer and allocator don't try to reschedule instructions, which seems to be required here.</div>
</div></blockquote><div><br></div><div style="">I think you're right. Looking at the instruction schedules before register allocation, shows that it's scheduling the load before the zero move in one case but not the other.</div>
<div style=""><br></div><div style="">Is there an easy way I can trick the scheduler into putting these in the right order? Perhaps by adding a scheduling dependency between the move and the load?</div></div></div></div></blockquote><br></div><div>You can try hacking the SelectionDAG scheduler to "AddGlue" between the constant move and load. See ScheduleDAGSDNodes.cpp.</div><div><br></div><div>You can also try using an ISEL pseudo instr. I think it's "usesCustomInsert=1".</div><div><br></div><div>Maybe someone else has a better idea…</div><div><br></div><div>FYI: I've been hoping to add a copy removal feature to the MachineScheduler pass, which is a currently disabled pass. It could cleanup in these situations. However, in this case ISEL should really just emit things in the right order.</div><div><br></div><div>-Andy</div><br></body></html>