[LLVMdev] keeping instructions in order and hidden dependencies

[reed kotler]

I have some pseudos that I am expanding in the Mips 16 port. Currently 
they are blasted in one chunk as a multi line instruction sequence but I 
am changing the code now to expand them
after register allocation.

They are essentially macros and I need to make sure, at this time at 
least, that the individual instructions are not reordered or moved around.

There are dependencies sometimes between the instructions that I'm not 
sure how to tell LLVM about.

For example, this first one is a two instruction macro where register T8 
is implicitly set by the first instruction and used by the second 
instruction.

T8 is not a mips16 registers but some instructions use it implicitly and 
it can function as
a condition code register.

In this first case, I do a compare (CMP) and the result sets T8 and then 
the branch instruction following it uses this as if it were a condition 
code register.

Maybe I can just set first instruction as defining T8 and the second as 
using it for the last time.

Without this expansion, this is not an issue.

At some future time it might be possible to reuse this condition 
register later and move it around but for now I'm not needing that 
optimization.

Tia.

Reed