[LLVMdev] help with X86 DAG->DAG Instruction Selection

[Peng Cheng]

Hi Nadav,

Bug is reported with test cases.  see
http://llvm.org/bugs/show_bug.cgi?id=15124 .

Please let me know if you have any thought on this.

Thanks,
-Peng

On Friday, February 8, 2013, Nadav Rotem wrote:

> Hi Peng,
>
> Can you please open a bugzilla and attache the LL file ? Can you please
> reproduce it on ToT ?
>
> Thanks,
> Nadav
>
> On Feb 7, 2013, at 9:08 PM, Peng Cheng <gm4cheng at gmail.com> wrote:
>
> > I have an llvm  ir, which generates the following machine code using llc
> (llvm 3.0 on win32) after # *** IR Dump After X86 DAG->DAG Instruction
> Selection ***:
> >
> > The first three lines and the last two lines alone together are used to
> compute "sin" for some double number.
> >
> > - line 1: move the stack pointer down 8
> > - line 2: copy the updated stack pointer to a base register
> > - line 3: copy a double number to location pointed by the base register
> >
> > - line end-1: to the last call "sin" to compute the result
> > - line end: move the stack pointer up 8
> >
> > The problem is that there are many other instructions inserted between
> them, and these instructions include stack allocations.  This causes:
> >
> > 1. "sin" function gets the wrong value to compute because the stack
> pointer moves and wrong value is received.
> > 2. the function call after line end could get wrong values because after
> line end the stack pointer is pointing to useful data.
> >
> > Could anyone working on x86 instruction selection give some pointers to
> prevent this?
> >
> > Thanks,
> > -Peng
> >
> >
> >       ADJCALLSTACKDOWN32 8, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>,
> %ESP<imp-use>                       ; line 1
> >       %vreg187<def> = COPY %ESP; GR32:%vreg187
>                                                                     ; line 2
> >       MOVSDmr %vreg187, 1, %noreg, 0, %noreg, %vreg36; mem:ST8[Stack]
> GR32:%vreg187 FR64:%vreg36               ; line 3
> >       %vreg188<def> = MOV32rm %vreg112, 1, %noreg, 252, %noreg;
> mem:LD4[%108] GR32:%vreg188,%vreg112
> >       %vreg189<def> = MOV32rm %vreg112, 1, %noreg, 256, %noreg;
> mem:LD4[%111] GR32:%vreg189,%vreg112
> >       %vreg190<def> = MOVSDrm <fi#0>, 1, %noreg, 120, %noreg;
> mem:LD8[%85] FR64:%vreg190
> >       %vreg191<def> = MOVSDrm <fi#0>, 1, %noreg, 96, %noreg;
> mem:LD8[%87] FR64:%vreg191
> >       %vreg192<def> = MOVSDrm <fi#0>, 1, %noreg, 88, %noreg;
> mem:LD8[%92] FR64:%vreg192
> >       %vreg193<def> = MOVSDrm <fi#0>, 1, %noreg, 24, %noreg;
> mem:LD8[%89] FR64:%vreg193
> >       %vreg194<def> = MOVSDrm <fi#0>, 1, %noreg, 80, %noreg;
> mem:LD8[%94] FR64:%vreg194
> >       %vreg195<def> = MOV32ri 8; GR32:%vreg195
> >       %EAX<def> = COPY %vreg195; GR32:%vreg195
> >       WIN_ALLOCA %EAX<imp-def,dead>, %ESP<imp-def,dead>,
> %EFLAGS<imp-def,dead>, %ESP<imp-use>
> >       %vreg196<def> = COPY %ESP; GR32:%vreg196
> >       MOV32mr %vreg196, 1, %noreg, 0, %noreg, %vreg16; mem:ST4[%114]
> GR32:%vreg196,%vreg16
> >       %vreg197<def> = MOV32ri 72; GR32:%vreg197
> >       %EAX<def> = COPY %vreg197; GR32:%vreg197
> >       WIN_ALLOCA %EAX<imp-def,dead>, %ESP<imp-def,dead>,
> %EFLAGS<imp-def,dead>, %ESP<imp-use>
> >       %vreg198<def> = COPY %ESP; GR32:%vreg198
> >       MOVSDmr %vreg198, 1, %noreg, 56, %noreg, %vreg194;
> mem:ST8[%116+56] GR32:%vreg198 FR64:%vreg194
> >       MOVSDmr %vreg198, 1, %noreg, 64, %noreg, %vreg17; mem:ST8[%116+64]
> GR32:%vreg198 FR64:%vreg17
> >       MOVSDmr %vreg198, 1, %noreg, 48, %noreg, %vreg192;
> mem:ST8[%116+48] GR32:%vreg198 FR64:%vreg192
> >       MOVSDmr %vreg198, 1, %noreg, 32, %noreg, %vreg191;
> mem:ST8[%116+32] GR32:%vreg198 FR64:%vreg191
> >       MOVSDmr %vreg198, 1, %noreg, 24, %noreg, %vreg36; mem:ST8[%116+24]
> GR32:%vreg198 FR64:%vreg36
> >       MOVSDmr %vreg198, 1, %noreg, 16, %noreg, %vreg190;
> mem:ST8[%116+16] GR32:%vreg198 FR64:%vreg190
> >       MOVSDmr %vreg198, 1, %noreg, 8, %noreg, %vreg190; mem:ST8[%116+8]
> GR32:%vreg198 FR64:%vreg190
> >       MOVSDmr %vreg198, 1, %noreg, 0, %noreg, %vreg190; mem:ST8[%116]
> GR32:%vreg198 FR64:%vreg190
> >       %vreg199<def> _______________________________________________
> > LLVM Developers mailing list
> > LLVMdev at cs.uiuc.edu <javascript:;>         http://llvm.cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130208/e9ea68cb/attachment.html>