[LLVMdev] [global-isel] Type-independence of load/store

[Daniel Sanders]

> > Other big-endian targets may have similar issues, but I know virtually
> > nothing about them.
> 
> ARM's is an interesting implementation of big-endian vectors. AFAIK, other
> architectures go all in and use both big-endian lanes and elements. That
> makes the problem go away, and you only need one load instruction.

The recently published MIPS SIMD Architecture (MSA) has the same issue for big-endian vectors. There's a small non-functional benefit to accounting for this in little-endian too. For little-endian mode, the emitted code is a bit easier to understand if the 'correct' loads and stores are used.

Daniel Sanders
Leading Software Design Engineer, MIPS Processor IP
Imagination Technologies Limited
www.imgtec.com