[LLVMdev] [global-isel] Type-independence of load/store

[Tim Northover]

> ARM’s is an interesting implementation of big-endian vectors.
> AFAIK, other architectures go all in and use both big-endian
> lanes and elements. That makes the problem go away, and you
> only need one load instruction.

Hmm, I suppose the "cost" is that any instruction referring to lanes
has to behave differently under big and little endian conditions. Not
an issue if you only support one, of course.

> Note that LLVM IR requires a bitcast to be equivalent to storing one
> type and loading the other, and it seems that this would turn a
> bitcast into a kind of shuffle.

Interesting. We'll have some fun if we ever try that, I think!

Tim.