[LLVMdev] use of ARM GPRPair register class

[Jakob Stoklund Olesen]

On Apr 23, 2013, at 7:53 PM, "Ana Pazos" <apazos at codeaurora.org> wrote:

> Hi,
>  
> I am experimenting with creating instructions that write into virtual registers that use the ARM GPRPair register class in Pre-RA phase.
>  
> During register allocation, I hit an assertion because the code is not in SSA form:
>  
> lib/CodeGen/MachineRegisterInfo.cpp:271: llvm::MachineInstr* llvm::MachineRegisterInfo::getVRegDef(unsigned int) const: Assertion `(I.atEnd() || llvm::next(I) == def_end()) && "getVRegDef assumes a single definition or no definition"' failed.
>  
> The code in lib\CodeGen\MachineRegisterInfo.cpp has information about the virtual register’s sub-register been written, but that info is not propagated to getVRegDef.
>  
> Is it possible/ is there any plan to update the code analysis to distinguish virtual register’s sub-registers definitions? So that GPRPair sub-registers can be used by instructions that do not return 64 bit value?

No, the code before register allocation must be in SSA form. That means every virtual register has one def, whether it is a sub-register def or not. The machine code verifier should tell you this loudly.

You should be able to use REG_SEQUENCE and/or INSERT_SUBREG to do what you want while preserving SSA form.

/jakob

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