[LLVMdev] Generate addi 40, r3 instruction

[Tim Northover]

Hi Vikram,

The error message would be helpful, but the most likely problem is the
duplication of $dst. It should probably be:

def ADDI : F1<opcode, (outs IntRegs:$dst), (ins IntRegs:$src, i32imm:$imm)
                      "addi $imm, $dst",
                      [(set $IntRegs:$dst, (add $IntRegs:$src, i32imm:$c))]> {
  let Constraints = "$src = $dst";
}

i.e. separate registers, but a constraint noting that they're actually
the same thing.

Tim.