[LLVMdev] Generate addi 40, r3 instruction

[Vikram Singh]

I want to generate the instruction like
    addi 40, r3          ! i.e. r3 = r3 + 40

The format i wrote is
def ADDI : F1<opcode, (outs IntRegs:$dst), (ins IntRegs:$dst, i32imm:$imm)
                      "addi $imm, $dst", 
                      [(set $IntRegs:$dst, (add $IntRegs:$dst, i32imm:$c))]


but it is not compiling.

what should be the format.

vikram



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