[LLVMdev] Need Help Understanding Operands in X86 MachineFunctionPass

[John Criswell]

Dear All,

I'm working on an X86 MachineFunctionPass that adds prefetch 
instructions to a function.  I have code that adds a "prefetchnta 
<constant address>" instruction to x86 32-bit code.  What I want to do 
is to add a "prefetchnta <constant address>" instruction to x86_64 code.

The code for adding the 32-bit instruction is:

BuildMI(MBB,MI,dl,TII->get(X86::PREFETCHNTA)).addReg(0).addImm(0).addReg(0).addImm(<constant>).addReg(0);

The code above doesn't work for x86_64, so I think I need to change the 
operands to the instruction.  However, I have no idea what the different 
register and immediate arguments to this instruction represent.  Do they 
somehow encode the Mod/RM bits used in x86 instruction encoding?  Are 
they offset and register operands?  I've checked the TableGen files, but 
their meaning appears cryptic to me.

Can someone explain to me what these operands are meant to represent?

Thanks in advance,

-- John T.