[LLVMdev] X86 Tablegen Description and VEX.W

[Cameron McInally]

On Wed, Nov 7, 2012 at 10:52 PM, Anitha Boyapati
<anitha.boyapati at gmail.com>wrote:
...

> For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and
> "MemOp4" like those of "rm" or "rr" ?
>

Hey Anitha,

The VEX.W bit is used to denote operand order. In other words, this bit
allows for a memop to be used as either the second or third source operand
of an FMA instruction, offering greater flexibility.

To conceptualize:

VFMADDSD xmm1, xmm2, xmm3/mem64, xmm4   VEX.W == 0
VFMADDSD xmm1, xmm2, xmm3, xmm4/mem64   VEX.W == 1

So, logically, one could create the rr pattern with the VEX.W bit set or
not.

The MemOp4 flag is a similar mechanism for setting the ModRM
byte, indicating that the second and third source operands have been
swapped.

-Cameron
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