[LLVMdev] X86 Tablegen Description and VEX.W

[Anitha Boyapati]

Hi,

A question from r162999 changes:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFMA.td?r1=162999&r2=162998&pathrev=162999

For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and
"MemOp4" like those of "rm" or "rr" ?

multiclass fma4s< >
...
  def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst),
           (ins RC:$src1, x86memop:$src2, RC:$src3),
           !strconcat(OpcodeStr,
           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
           [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>;
...


It seems that previous revisions for fma4 intrinsics also followed
similar trend. Any idea why?



--
 Anitha