[LLVMdev] instructions requiring specific physical registers for operands

[Anton Korobeynikov]

Jim,

> The an instruction that uses R0 and R1 as fixed input registers and R2 for output could define itself using those register classs:
> def myInst : baseclass<…, (outs GPRr2:$dst), (ins GPRr0:$src1, GPRr1:$src2), …>
> Use those reg classes in pattern to match also, and things should just work. The register allocator can take care of any reg-to-reg copies that are required.
As far as I understand Jonas, this does not work in his case...

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University