[LLVMdev] instructions requiring specific physical registers for operands

[Jim Grosbach]

On May 9, 2012, at 4:27 AM, Anton Korobeynikov wrote:

> Hello Jonas,
> 
>> I wonder, what would be the best solution for instructions that require
>> operands in a particular register, and even gives the result in a particular
>> register?
> You need to custom select such instruction. See e.g. div / idiv on x86
> as an example.

That's often easiest, yes; however, if they're normal allocatable registers, you may be able to define a register class containing only the fixed register then defining the instruction(s) using those as operands.

Something like, for a 32-bit register for target FOO:
def GPRr0 : RegisterClass<"FOO", [i32], 32, (add R0)>;
def GPRr1 : RegisterClass<"FOO", [i32], 32, (add R1)>;
def GPRr2 : RegisterClass<"FOO", [i32], 32, (add R2)>;

The an instruction that uses R0 and R1 as fixed input registers and R2 for output could define itself using those register classs:
def myInst : baseclass<…, (outs GPRr2:$dst), (ins GPRr0:$src1, GPRr1:$src2), …>
Use those reg classes in pattern to match also, and things should just work. The register allocator can take care of any reg-to-reg copies that are required.

-Jim