[LLVMdev] Request for merge: GHC/ARM calling convention.

[Karel Gardas]

Hi Renato,

On 06/25/12 12:13 AM, Renato Golin wrote:
> Hi Karel,
>
> I understand this patch has already been merged (to 3.0), so don't
> take my question as stopping the merge to head, I'm just making sure I
> got it right... The rest looks correct.
>
> +  CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
> +  CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
> +  CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
>
> Does this mean that for floating point support in GHC, you need VFP registers?

Yes and no. Shortly: original GHC/ARM/LLVM port was done by Stephen on 
ARMv5/Qemu IIRC. I've later added whole VFP support and ARMv7 support. 
The code in GHC is properly #ifdefed, so if there is no VFP available on 
pre ARMv6, then it's not used. ie. GHC STG floating points regs are then 
allocated in RAM instead of real hardware regs.

> I don't know much how tablegen would work in this case, but I'd expect
> it to break during codegen (with a horrid error message) if you try to
> compile that to an ARMv4-ish core.

I'm not sure I understand you right here, but if you look into 
ARMCallingConv.td file, you will see that exactly the same statements 
are used in FastCC_ARM_APCS so I think if it's going to be broken, then 
the GHC calling convention is not the only culprit here. Or are you 
talking about actual compilation for the target platform?

Anyway, I think majority of GHC/ARM related work will be done on ARMv7 
if it makes you less nervous about the patch.

Thanks,
Karel