[LLVMdev] Back-end: how to test all lowering condition

[Christian Nastasi]

Dear Tom,
thank you for your reply. What you suggest is something I was considering doing, however there still no solution to my Problem2. How do I test the ISD  instructions if I can only write IR instructions?

-----Original Message-----
From: Tom Stellard [mailto:thomas.stellard at amd.com]
Sent: Wednesday, June 20, 2012 4:14 PM
To: Christian Nastasi
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Back-end: how to test all lowering condition

On Wed, Jun 20, 2012 at 01:50:51PM +0000, Christian Nastasi wrote:
> Dear All,
> I am working on a back-end implementation for a new architecture which is provided with its own assembler.
> I am currently capable of writing most of the lowering process to generate a decent assembly code.
> Under certain circumstances, i.e. depending on the C code, some IR instructions generate a Selection DAG for which I am not implementing a proper lowering, thus resulting in the well-known "cannot select" error.
> I guess this is because I have not implemented all possible instructions defined in the Selection DAG, those declared in include/llvm/CodeGen/ISDOpcodes.h, which apparently are different from those declared in the IR.
>
> Problem1: how can I know the complete list of ISD:: instruction (SelectionDAG) I have to implement (either by promoting, customizing and expanding)?
> A possible solution is to implement all of them, taking the list defined in the file mentioned above or taking the list from an already existing target (e.g. MSP430 Mips).
>

The complete list of ISD opcodes is located in include/llvm/CodeGen/ISDOpcodes.h, as far as I know you need to handle all of them, however some of these are handled for you in the TargetLowering constructor in lib/CodeGen/SelectionDAG/TargetLowering.cpp.

-Tom
> Problem2: even if I implement the complete list, how can I test it? I cannot write a .ll file containing directly the ISD:: instruction, but rather IR one that causes the former to appear in the SelectionDAG. In such case, what is the relationship between IR instructions and ISD:: ones?
>
> Note to problem2: test/CodeGen/MSP430/setcc.ll is an example of test the uses the IR instruction "icmp" to generate the "setcc" SelectionDAG instruction.
>
> Thank you all in advance for any suggestion you may give.
> Cheers,
> Christian.
>
>
> -------------- This e-mail and any attachments may contain privileged or confidential information of ALES S.r.l. This e-mail is intended solely for the use of the individual or entity to which it is addressed. If you are not the intended recipient of this e-mail, you are hereby notified that any copying, distribution, dissemination or action taken in relation to the contents of this e-mail and any of its attachments is strictly prohibited and may be unlawful. If you have received this e-mail in error, please notify the sender immediately and permanently delete the original e-mail and destroy any copies or printouts of this e-mail as well as any attachments.
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>



-------------- This e-mail and any attachments may contain privileged or confidential information of ALES S.r.l. This e-mail is intended solely for the use of the individual or entity to which it is addressed. If you are not the intended recipient of this e-mail, you are hereby notified that any copying, distribution, dissemination or action taken in relation to the contents of this e-mail and any of its attachments is strictly prohibited and may be unlawful. If you have received this e-mail in error, please notify the sender immediately and permanently delete the original e-mail and destroy any copies or printouts of this e-mail as well as any attachments.