[LLVMdev] Vector promotion broken for <2 x [i8|i16]>

[Villmow, Micah]

No, that is correct. I am adding the new types so that I can bitcast v2i8 into a v1i16 and then perform the 'and' operation and have legalize types turn the v1i16 into a scalar.

Though I am having trouble in understanding how  x86 supports the <1 x i64> type. Based on looking at the code, it should fail because v1i64 is not supported on the x86 platform as far as I can tell.

Micah

From: Rotem, Nadav [mailto:nadav.rotem at intel.com]
Sent: Saturday, July 28, 2012 12:56 PM
To: Villmow, Micah; Developers Mailing List
Subject: RE: Vector promotion broken for <2 x [i8|i16]>

I think that you attached the wrong patch. The attached patch is the one which adds the new MVT types.



From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah
Sent: Saturday, July 28, 2012 01:54
To: Developers Mailing List
Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]>

Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp.
The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues.

This can be reproduced by setting in any target:
setOperationAction(ISD::AND, MVT::i8, Promote);
setOperationAction(ISD::AND, MVT::v2i8, Promote);
setOperationAction(ISD::AND, MVT::i16, Promote);

Let me know if this is good,
Micah

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