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<p class="MsoNormal"><span style="color:#1F497D">No, that is correct. I am adding the new types so that I can bitcast v2i8 into a v1i16 and then perform the ‘and’ operation and have legalize types turn the v1i16 into a scalar.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">Though I am having trouble in understanding how x86 supports the <1 x i64> type. Based on looking at the code, it should fail because v1i64 is not supported on the x86 platform as far as I can tell.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">Micah<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Rotem, Nadav [mailto:nadav.rotem@intel.com]
<br>
<b>Sent:</b> Saturday, July 28, 2012 12:56 PM<br>
<b>To:</b> Villmow, Micah; Developers Mailing List<br>
<b>Subject:</b> RE: Vector promotion broken for <2 x [i8|i16]><o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><span style="color:#1F497D">I think that you attached the wrong patch. The attached patch is the one which adds the new MVT types.
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> llvmdev-bounces@cs.uiuc.edu [mailto:llvmdev-bounces@cs.uiuc.edu]
<b>On Behalf Of </b>Villmow, Micah<br>
<b>Sent:</b> Saturday, July 28, 2012 01:54<br>
<b>To:</b> Developers Mailing List<br>
<b>Subject:</b> [LLVMdev] Vector promotion broken for <2 x [i8|i16]><o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp.<o:p></o:p></p>
<p class="MsoNormal">The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">This can be reproduced by setting in any target:<o:p></o:p></p>
<p class="MsoNormal">setOperationAction(ISD::AND, MVT::i8, Promote);<o:p></o:p></p>
<p class="MsoNormal">setOperationAction(ISD::AND, MVT::v2i8, Promote);<o:p></o:p></p>
<p class="MsoNormal">setOperationAction(ISD::AND, MVT::i16, Promote);<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Let me know if this is good,<o:p></o:p></p>
<p class="MsoNormal">Micah<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Courier New"">---------------------------------------------------------------------<br>
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