[LLVMdev] X86 sub_ss and sub_sd sub-register indexes

[dag at cray.com]

Jakob Stoklund Olesen <jolesen at apple.com> writes:

> These sub-registers are special, they are only mentioned here:
>
>   let CompositeIndices = [(sub_ss), (sub_sd)] in {
>   def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
>   def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
>   ...

I'm confused.  Below you note that they are used in patterns, so they
are certainly mentioned more than just in the code above.

> As far as I can tell, all sub-register operations involving sub_ss and
> sub_sd can simply be replaced with COPY_TO_REGCLASS:
>
>   def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
>             (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
>                                                    sub_sd))>;
>
> Becomes:
>
>   def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
>             (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;

A few questions:

Will COPY_TO_REGCLASS actually generate a copy instruction or can
TableGen/isel fold it away?

What happens if the result of the above pattern using COPY_TO_REGCLASS
is spilled?  Will we get a 64-bit store or a 128-bit store?

                                -Dave