[LLVMdev] X86 sub_ss and sub_sd sub-register indexes

[Jakob Stoklund Olesen]

All,

I've been trying to simplify the way LLVM models sub-register relationships a bit, and the X86 sub_ss and sub_sd sub-register indices are getting in the way. I want to get rid of them.

These sub-registers are special, they are only mentioned here:

  let CompositeIndices = [(sub_ss), (sub_sd)] in {
  def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
  def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
  ...

This secret syntax means that the indexes are idempotent:

  getSubReg(YMM0, sub_ss) --> XMM0
  getSubReg(XMM0, sub_ss) --> XMM0

They are supposed to represent the 32-bit and 64-bit low parts of the xmm registers, but since we don't define explicit registers for those sub-registers, we are left with idempotent sub-register indexes.

We have three different register classes for the xmm registers: FR32, FR64, and VR128. The sub_ss and sub_sd indexes used to play a role in selecting the right register class, but not any longer. That is all derived from the instruction descriptions now.

As far as I can tell, all sub-register operations involving sub_ss and sub_sd can simply be replaced with COPY_TO_REGCLASS:

  def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
            (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
                                                   sub_sd))>;

Becomes:

  def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
            (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;

By eliminating these indexes, I can remove the 'CompositeIndices' syntax and TableGen's handling of loops in the sub-register graph. I can assert that every sub-register has a unique name, and that can be used to compress tables a bit more.

/jakob