[LLVMdev] [RFC] Remat Enhancements

[Jakob Stoklund Olesen]

On Feb 23, 2012, at 8:14 AM, David Greene <dag at cray.com> wrote:

> I have a set of changes that enhances rematerialization to handle more
> kinds of loads, specifically loads with multiple address registers.
> This is a big win for some codes on x86.

That's great, but I really wish you would discuss the design of these things publicly, and not develop features on long-running secret branches. If you secretly start out in the wrong direction, you could be wasting a lot of your time.

> I plan to send these up ASAP but I want to solicit a bit of guidance
> first.
> 
> The change requires that live interval analysis be able to determine
> whether and instruction is a load and whether an instruction writes to
> memory.

Just use MI->mayLoad(), MI->mayStore().

[And live interval analysis shouldn't be involved in remat these days.]

> The remat code itself identifies load instructions and checks to see
> whether it interferes with any instructions that write to memory.

How does that affect compile time?

> Finally, are MachineMemOperands guaranteed (modulo bugs, of course) to
> be preserved at least through regalloc?

They are preserved, but they are not 'guaranteed'.  A load or store with missing memops should conservatively be treated as volatile, aliasing everything.

/jakob