[LLVMdev] [RFC] Remat Enhancements

[David Greene]

I have a set of changes that enhances rematerialization to handle more
kinds of loads, specifically loads with multiple address registers.
This is a big win for some codes on x86.

I plan to send these up ASAP but I want to solicit a bit of guidance
first.

The change requires that live interval analysis be able to determine
whether and instruction is a load and whether an instruction writes to
memory.  Here's how I've handled these two questions:

- Add an isLoad member to TargetInstrInfo with a corresponding
  implementation in the X86 target consisting of a switch on all
  of the load-type opcodes.  By default isLoad returns false so
  that false negatives are possible.

- Add a writesMemory member to TargetInstrInfo with a corresponding
  implementation in the XD86 target.  The target implemenmtation is both
  a switch on store-type opcodes and a check to see whether a
  MachineInstr has write-type MachineMemOperands.  The default
  implementation returns "false" but "true" might be a safer default
  (false positives).

The remat code itself identifies load instructions and checks to see
whether it interferes with any instructions that write to memory.

Are isLoad and writesMemory reasonable implementations of these queries?
Are there other routes that might be better?  I'm particularly
interested in opinions about false positives/negatives.  What's the safe
default?  In either case comments must indicate the possibility of
"incorrect" answers.

Finally, are MachineMemOperands guaranteed (modulo bugs, of course) to
be preserved at least through regalloc?

                                 -Dave