[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
Fabian Scheler
fabian.scheler at gmail.com
Tue Aug 21 06:40:25 PDT 2012
2012/8/21 Anton Korobeynikov <anton at korobeynikov.info>:
>> This isn't really my area of expertise, but I think you're messing up
>> your RegisterClass definition. Look at how ARM defines DTriple.
> DTriple is untyped :) , because we do not have any valut type which
> defines 3xi64.
> However, the paired register needs to have type.
>
> Fabian, what are the definitions of ER and DR register classes?
Hi Anton,
here are the definitions of these register classes:
// Data register class
def DR : RegisterClass<"TriCore", [i32], 32,
(add D0, D1, D2, D3, D4, D5, D6, D7,
D8, D9, D10, D11, D12, D13, D14, D15)>;
// Extended-size data register class
def ER : RegisterClass<"TriCore", [i64], 32,
(add E0, E2, E4, E6, E8, E10, E12, E14)> {
let SubRegClasses = [(DR sub_even, sub_odd)];
}
And the DX and EX registers are defined this way:
def D0 : TriCoreReg<0, "d0">, DwarfRegNum<[0]>;
...
def D15 : TriCoreReg<15, "d15">, DwarfRegNum<[15]>;
def E0 : TriCoreRegWithSubregs<0, "e0", [D0, D1]>, DwarfRegNum<[32]>;
def E2 : TriCoreRegWithSubregs<2, "e2", [D2, D3]>, DwarfRegNum<[33]>;
...
def E14 : TriCoreRegWithSubregs<14, "e14", [D14, D15]>, DwarfRegNum<[39]>;
Ciao, Fabian
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