[LLVMdev] Newbie Question: How are the values set in a Sparc store instruction (e.g. STri)?

[Stephen McGruer]

I'm a bit confused as to how some of the values in a Sparc store
instruction actually come to be set. The Sparc backend defines a store as:

def STri  : F3_2<3, 0b000100,
                 (outs), (ins MEMri:$addr, IntRegs:$src),
                 "st $src, [$addr]",
                 [(store IntRegs:$src, ADDRri:$addr)]>;

F3_2 and it's superclasses are defined as follows:

class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr,
pattern> {
  bits<13> simm13;

  let op         = opVal;
  let op3        = op3val;

  let Inst{13}   = 1;     // i field = 1
  let Inst{12-0} = simm13;
}

class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
    : InstSP<outs, ins, asmstr, pattern> {
  bits<5> rd;
  bits<6> op3;
  bits<5> rs1;
  let op{1} = 1;   // Op = 2 or 3
  let Inst{29-25} = rd;
  let Inst{24-19} = op3;
  let Inst{18-14} = rs1;
}

class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> :
Instruction {
  field bits<32> Inst;

  let Namespace = "SP";

  bits<2> op;
  let Inst{31-30} = op;

  dag OutOperandList = outs;
  dag InOperandList = ins;
  let AsmString   = asmstr;
  let Pattern = pattern;
}

I cannot see how the values simm13, rd, and rs1 are actually set. While in
some places in the .td file there are instructions prefixed with "let rd =
...", the store instructions are not. How do the register
numbers/immediates get from $src and $addr to the relevant places in Inst?

Stephen
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