[LLVMdev] sitofp inst selection in x86/AVX target [PR9473]

[Syoyo Fujita]

Hello LLVMer's

I am now trying to fix a bug PR9473.

sitofp instruction in LLVM IR is converted to vcvtsi2sd(also applied
to vcvtsi2ss case) for x86/AVX backend, but vcvtsi2sd is somewhat odd
instruction format.

VCVTSI2SD xmm1, xmm2, r/m32
VCVTSI2SD xmm1, xmm2, r/m64

bits(127:64) of xmm2 is copied to corresponding bits of xmm1, thus in
many case xmm1 and xmm2 could be same register.

Currently, the definition of VCVTSI2SD in X86InstrSSE.td expects 3
operand(1 dst, 2 srcs). This is OK for asm parser, but NG for LLVM IR
inst selection since sitofp instruction dag just takes 1 dst and 1
src.

I am not so familiar with .td format yet, but after some investigation
I found it seems impossible to share .td definition of vcvtsi2sd for
asm parser and isel.

I got success by defining separate .td definition for VCVTSI2SD to fix
bug PR9473: define new definition of VCVTSI2SD for isel in
isAsmParserOnly = 0 block and move existing VCVTSI2SD definition from
isAsmParserOnly = 0 into isAsmParserOnly = 1 block so that existing
VCVTSI2SD definition takes effect only in asm parser.

Example solution is as follows.

lib/Target/X86/x86InstrSSE.td

...

multiclass sse12_vcvt_avx_s<bits<8> opc, RegisterClass SrcRC,
RegisterClass DstRC,
                     SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
                     string asm> {
  def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
                        [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
  def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
                        [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
}

let isAsmParserOnly = 0 in {
  defm SInt_VCVTSI2SD : sse12_vcvt_avx_s<0x2A, GR32, FR64, sint_to_fp, i32mem,
                       loadi32, "cvtsi2sd\t{$src, $dst, $dst|$dst,
$dst, $src}">,
                       XD, VEX;
  ...
}

let isAsmParserOnly = 1 in {
  defm VCVTSI2SD   : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
                                  VEX_4V;
  ...
}

If this style of modification is OK for people working on x86/AVX .td,
I am ready to provide a patch.
Or is there any better way?

--
Syoyo