[LLVMdev] Instr Description Problem of MCore Backend

[zhangzuyu]

Hi, all:

Now I'm working on writing a backend for Moto MCore, but I don't know how to
describe some instructions.

First, I've already written MCoreRegisterInfo.td like these:

class MCoreReg<bits<4> num, string name> : Register<name> {
  let Namespace = "MCore";
  field bits<4> Num = num;
}

def R0  : MCoreReg< 0,  "R0">, DwarfRegNum<[ 0]>;
...
def R15 : MCoreReg<15, "R15">, DwarfRegNum<[15]>;


Then, I wrote MCoreInstrFormats.td:

class MCoreInst<dag outs, dag ins, string asmstr, list<dag> pattern> :
Instruction {
  field bits<16> Inst;

  let Namespace = "MCore";

  dag OutOperandList = outs;
  dag InOperandList  = ins;
  let AsmString      = asmstr;
  let Pattern        = pattern;
}

// Base Plus Index Addressing Mode
class MABase<dag outs, dag ins, string asmstr, list<dag> pattern>
    : MCoreInst<outs, ins, asmstr, pattern> {
  bits<2> subOp;
  bits<4> Rx;

  let Inst{15-6}= { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
  let Inst{5-4}  = subOp;
  let Inst{3-0}  = Rx;
}

// Load/Store Register Quadrant Mode
class QuadR<bits<2> subOpVal, dag outs, dag ins, string asmstr,
               list<dag> pattern> : MABase<outs, ins, asmstr, pattern> {

  let subOp = subOpVal;
}

// Load/Store Multiple Register Mode
class MultR<bits<2> subOpVal, dag outs, dag ins, string asmstr,
               list<dag> pattern> : MABase<outs, ins, asmstr, pattern> {

  let subOp = subOpVal;
}


Finally, I don't know how to describe following instructions in
MCoreInstrInfo.td, because of its variable ins/outs. Or what other files
should I use to finish this description?

// LDQ, STQ, LDM and STM are Mapping Error

// Load/Store Register Quadrant Mode
def LDQ : QuadR<0x0, // FIXME p81
                (outs GPRs:$Rx), (ins GPRs:R4, GPRs:R5, GPRs:R6, GPRs:R7),
                "ldq R4-R7, ($Rx)", []>;
def STQ : QuadR<0x1,
                (outs GPRs:R4, GPRs:R5, GPRs:R6, GPRs:R7), (ins GPRs:$Rx),
                "stq R4-R7, ($Rx)", []>;

// Load/Store Multiple Register Mode
def LDM : MultR<0x2, // FIXME p80
               (outs GPRs:R0), (ins GPRs:$Rf),
               "ldm $Rf-R15, (R0)", []>;
def STM : MultR<0x3, // FIXME p109
               (outs GPRs:$Rf), (ins GPRs:R0),
               "stm $Rf-R15, (R0)", []>;


Info below comes from MCore Programmers Reference Manual:

LDQ - Load Register Quadrant from Memory
    Operation:
                       Destination registers ← memory;
    Assembler Syntax:
                        ldq r4–r7,(rx)
    Description:
                       The ldq instruction is used to load four registers
(R4–R7) from memory.
                        Register X points to the location of the first
transfer. Registers are loaded in
                        increasing significance from ascending memory
locations. If register X is specified to be R4,
                        R5, R6, or R7, the instruction form is considered
invalid, and the results are undefined.
                        For valid instruction forms, register X is not
affected or updated.
    Condition Code:
                        Unaffected
    Instruction Fields:
                        Register X — Specifies the base address for the
transfers. Register X should not
                        specify R4, R5, R6, or R7.


LDM - Load Multiple Registers from Memory
     Operation:
                       Destination Registers ← Memory
     Assembler Syntax:
                       ldm rf–r15,(r0)
     Description:
                      The ldm instruction is used to load a contiguous range
of registers from the stack.
                       Register 0 (R0) serves as the base address pointer
for this form. Registers

         Rf–R15 are loaded in increasing significance from ascending memory
locations. Rf
         may not specify R0 or R15; these instruction forms are considered
illegal, although
         they are not guaranteed to be detected by hardware. For valid
instruction forms,
         register 0 (R0) is not affected or updated.

      Condition Code:

          Unaffected

     Instruction Fields:
                       Register First field — Specifies the first register
to be transferred. Only R1–R14 should be specified.


STM - Store Multiple Registers to Memory
    Operation:
                        Memory ← Source Registers
Assembler Syntax:
                         stm rf–r15,(r0)
  Description:
                        Store multiple registers to memory. The stm
instruction is used to transfer
                        a contiguous range of registers to the stack.
Register 0 (R0) serves as the base
                       address pointer for this form. Registers Rf –R15 are
stored in increasing significance
                       to ascending memory locations. Register 0 (R0) is not
affected/updated. Rf may not
                       specify R0 or R15; these instruction forms are
considered illegal, although they are
                       not guaranteed to be detected by hardware.
   Condition Code:
   Instruction Fields:  same to LDM


STQ - Store Register Quadrant to Memory
   Operation:
                       Memory ← Source Registers
   Assembler Syntax:
                        stq r4–r7,(rx)
   Description:
                        Store register quadrant to memory. The stq
instruction is used to transfer
                        the contents of four registers (R4–R7) to memory.
Register X points to the location
                        of the first transfer. Registers are stored in
increasing significance to ascending
                        memory locations. Register X is not affected or
updated. If register X is part of the
                        quadrant being transferred, the value stored for
this register is undefined.
  Condition Code:
   Instruction Fields:  same to LDQ


-- 
Yours truly,
Zhang Zuyu(张祖羽)

-----------------------------------------------------------
College of Computer Science and Technology, Harbin Engineering University
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