Hi, all:<div><br></div><div>Now I'm working on writing a backend for Moto MCore, but I don't know how to describe some instructions.</div><div><br></div><div>First, I've already written MCoreRegisterInfo.td like these:</div>
<div><br></div><blockquote class="webkit-indent-blockquote" style="margin: 0 0 0 40px; border: none; padding: 0px;"><div><div>class MCoreReg<bits<4> num, string name> : Register<name> {</div></div><div>
<div>
let Namespace = "MCore";</div></div><div><div> field bits<4> Num = num;</div></div><div><div>}</div></div><div><br></div><div>def R0 : MCoreReg< 0, "R0">, DwarfRegNum<[ 0]>;</div>
<div>...</div><div>def R15 : MCoreReg<15, "R15">, DwarfRegNum<[15]>;</div></blockquote><div><br></div><div>Then, I wrote MCoreInstrFormats.td:</div><div><br></div><blockquote class="webkit-indent-blockquote" style="margin: 0 0 0 40px; border: none; padding: 0px;">
<div><div>class MCoreInst<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {</div></div><div><div> field bits<16> Inst;</div></div><div><div><br></div></div><div><div> let Namespace = "MCore";</div>
</div><div><div><br></div></div><div><div> dag OutOperandList = outs;</div></div><div><div> dag InOperandList = ins;</div></div><div><div> let AsmString = asmstr;</div></div><div><div> let Pattern = pattern;</div>
</div><div><div>}</div></div><div><br></div><div><div><div><div>// Base Plus Index Addressing Mode</div><div>class MABase<dag outs, dag ins, string asmstr, list<dag> pattern></div><div> : MCoreInst<outs, ins, asmstr, pattern> {</div>
<div> bits<2> subOp;</div><div> bits<4> Rx;</div><div><br></div><div> let Inst{15-6}= { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };</div><div> let Inst{5-4} = subOp;</div><div> let Inst{3-0} = Rx;</div><div>}</div>
</div><div><br></div><div>// Load/Store Register Quadrant Mode</div><div>class QuadR<bits<2> subOpVal, dag outs, dag ins, string asmstr,</div><div> list<dag> pattern> : MABase<outs, ins, asmstr, pattern> {</div>
<div><br></div><div> let subOp = subOpVal;</div><div>}</div><div><br></div><div>// Load/Store Multiple Register Mode</div><div>class MultR<bits<2> subOpVal, dag outs, dag ins, string asmstr,</div><div> list<dag> pattern> : MABase<outs, ins, asmstr, pattern> {</div>
<div><br></div><div> let subOp = subOpVal;</div><div>}</div></div></div></blockquote><div><br></div><div>Finally, I don't know how to describe following instructions in MCoreInstrInfo.td, because of its variable ins/outs. Or what other files should I use to finish this description?</div>
<div><br></div><div><span class="Apple-style-span" style="background-color: rgb(255, 255, 102);">// LDQ, STQ, LDM and STM are Mapping Error</span></div><blockquote class="webkit-indent-blockquote" style="margin: 0 0 0 40px; border: none; padding: 0px;">
<div><div>// Load/Store Register Quadrant Mode</div></div><div><div>def LDQ : QuadR<0x0, // FIXME p81</div></div><div><div> (outs GPRs:$Rx), (ins GPRs:R4, GPRs:R5, GPRs:R6, GPRs:R7),</div></div><div><div>
"ldq R4-R7, ($Rx)", []>;</div></div><div><div>def STQ : QuadR<0x1,</div></div><div><div> (outs GPRs:R4, GPRs:R5, GPRs:R6, GPRs:R7), (ins GPRs:$Rx),</div></div><div><div> "stq R4-R7, ($Rx)", []>;</div>
</div><div><div><br></div></div><div><div>// Load/Store Multiple Register Mode</div></div><div><div>def LDM : MultR<0x2, // FIXME p80</div></div><div><div> (outs GPRs:R0), (ins GPRs:$Rf),</div></div><div>
<div> "ldm $Rf-R15, (R0)", []>;</div></div><div><div>def STM : MultR<0x3, // FIXME p109</div></div><div><div> (outs GPRs:$Rf), (ins GPRs:R0),</div></div><div><div> "stm $Rf-R15, (R0)", []>;</div>
</div></blockquote><div><br></div><div>Info below comes from MCore Programmers Reference Manual:</div><div><br></div><div><div>LDQ - Load Register Quadrant from Memory</div><div> Operation: </div><div> Destination registers ← memory;</div>
<div> Assembler Syntax: </div><div> ldq r4–r7,(rx)</div><div> Description: </div><div> The ldq instruction is used to load four registers (R4–R7) from memory.</div><div>
Register X points to the location of the first transfer. Registers are loaded in </div>
<div> increasing significance from ascending memory locations. If register X is specified to be R4,</div><div> R5, R6, or R7, the instruction form is considered invalid, and the results are undefined. </div>
<div> For valid instruction forms, register X is not affected or updated.</div><div> Condition Code:</div><div> Unaffected</div></div><div><div> Instruction Fields:</div>
<div> Register X — Specifies the base address for the transfers. Register X should not </div><div> specify R4, R5, R6, or R7.</div></div><div><br></div><div><br></div><div>LDM - Load Multiple Registers from Memory</div>
<div><div> Operation: </div><div> Destination Registers ← Memory</div><div> Assembler Syntax: </div><div> ldm rf–r15,(r0)</div><div> Description: </div><div>
The ldm instruction is used to load a contiguous range of registers from the stack. </div><div> Register 0 (R0) serves as the base address pointer for this form. Registers</div>
</div><blockquote class="webkit-indent-blockquote" style="margin: 0 0 0 40px; border: none; padding: 0px;"><div><div style="text-align: left;"> Rf–R15 are loaded in increasing significance from ascending memory locations. Rf</div>
</div><div><div style="text-align: left;"> may not specify R0 or R15; these instruction forms are considered illegal, although</div></div><div><div style="text-align: left;"> they are not guaranteed to be detected by hardware. For valid instruction forms, </div>
<div style="text-align: left;"> r<span class="Apple-style-span" style="background-color: rgb(255, 255, 255);">egister </span>0 (R0) is not affected or updated.</div></div></blockquote> Condition Code:<br><blockquote class="webkit-indent-blockquote" style="margin: 0 0 0 40px; border: none; padding: 0px;">
<div style="text-align: left;"><div style="text-align: left;"> Unaffected</div></div></blockquote><div><div><div> Instruction Fields:</div><div> Register First field — Specifies the first register to be transferred. Only R1–R14 should be specified.</div>
</div><div><br></div><div><br></div><div><div>STM - Store Multiple Registers to Memory</div><div> Operation: </div><div> Memory ← Source Registers</div><div>Assembler Syntax: </div><div> stm rf–r15,(r0)</div>
<div> Description: </div><div> Store multiple registers to memory. The stm instruction is used to transfer</div><div> a contiguous range of registers to the stack. Register 0 (R0) serves as the base</div>
<div> address pointer for this form. Registers Rf –R15 are stored in increasing significance</div><div> to ascending memory locations. Register 0 (R0) is not affected/updated. Rf may not</div>
<div> specify R0 or R15; these instruction forms are considered illegal, although they are</div><div> not guaranteed to be detected by hardware.</div></div><div> Condition Code:<div>
<div><div> Instruction Fields: same to LDM</div></div></div></div><div><br></div><div><br></div><div><div>STQ - Store Register Quadrant to Memory</div><div> Operation: </div><div> Memory ← Source Registers</div>
<div> Assembler Syntax: </div><div> stq r4–r7,(rx)</div><div> Description: </div><div> Store register quadrant to memory. The stq instruction is used to transfer</div><div>
the contents of four registers (R4–R7) to memory. Register X points to the location</div><div> of the first transfer. Registers are stored in increasing significance to ascending</div>
<div> memory locations. Register X is not affected or updated. If register X is part of the</div><div> quadrant being transferred, the value stored for this register is undefined.</div>
<div> Condition Code:</div><div> Instruction Fields: same to LDQ</div></div><div><br></div><br>-- <br><div><span style="font-family:arial, sans-serif;font-size:11px;background-color:rgb(255, 255, 255)">Yours truly,</span><br>
Zhang Zuyu(张祖羽)<br><br>-----------------------------------------------------------<br>College of Computer Science and Technology, Harbin Engineering University</div>
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