[LLVMdev] TableGen syntax for matching a constant load

[Joerg Sonnenberger]

On Sun, Feb 27, 2011 at 01:29:25AM +0100, Joerg Sonnenberger wrote:
> +let Predicates = [OptForSize] in {
> +def : Pat<(store (i32 0), addr:$dst), (AND32mi8 addr:$dst, 0)>;
> +def : Pat<(store (i32 0), addr:$dst), (AND32mi8 addr:$dst, 0)>;
> +def : Pat<(store (i64 -1), addr:$dst), (OR64mi8 addr:$dst, -1)>;
> +def : Pat<(store (i64 -1), addr:$dst), (OR64mi8 addr:$dst, -1)>;
> +}

All these patterns have one important downside. They are suboptimal if
more than one store happens in a row. E.g. the 0 store is better
expressed as xor followed by two register moves, if a register is
available... This is most noticable when memset() gets inlined

Joerg