[LLVMdev] TableGen syntax for matching a constant load

[Chris Lattner]

On Feb 25, 2011, at 7:27 PM, Joerg Sonnenberger wrote:

> Hi all,
> I'm trying to add a X86 pattern to turn
> 	movl $-1, %eax
> into
> 	orl $-1, $eax
> I can't find a way to express this in TableGen syntax though.
> 
> def : Pat<(set GR32:$src, (i32 -1)), (OR32ri8 GR32:$src, -1)>;
> 
> results in an assertion about 'Unknown Node'.

Hi Joerg,

This is problematic to define the obvious way because "orl" takes two inputs and produces an output, but this specific form of it ignores the inputs and just sets the register (and flags).

We can handle this by defining a new pseudo-op that just defines the register+flags.  Take a look at how "xor reg,reg" -> "mov 0, reg"  is done.  MOV32r0 is the place to start: MCInstLowering then turns it into the actual operation.

-Chris