[LLVMdev] Comments on the bundle proposal

[Krzysztof Parzyszek]

I just signed up to this mailing list so I don't have the original email
with the proposal to reply to.   I got the text forwarded to me though,
and here are my thoughts on it:

- The requirement that it should be easy for a pass to be oblivious to
bundles isn't well defined.  If this means that a pass should be able to
run as if the bundles weren't present, then such a pass can easily damage
the "bundling".  One could think of cases, where certain instruction sequences
should always stay together (idioms using larx/stcx. on PPC come to my mind).
If, on the other hand, it means that an "oblivious" pass should see a
bundle as if it was a single instruction, then the proposed solution
would not work, but it could be a reasonable requirement regardless.

Another approach would be to have a pseudo-instruction (say, "macro"),
which would be associated with a sequence of instructions, which have
been outlined, and which have been replaced by the "macro" instruction.
The "macro" instruction would have the information about registers used
and defined, and it would have a link to the actual instructions that
define it.

- How about having bundles that contain branch targets (other than the
first instruction) from the outside of the bundle?  This seems like something
that has a potential for causing trouble, but I can't think of any specific
scenario at the moment.

- It should be possible to use bundles to enclose only some selected code
sequences, as opposed to having every instruction belong to some bundle.


Regards,
-Krzysztof

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