[LLVMdev] RFC: Machine Instruction Bundle

Anshuman Dasgupta adasgupt at codeaurora.org
Tue Dec 6 08:06:40 PST 2011

>  What about instruction scheduling? Has anyone thought how/if isched could work
>  with parallel bundles? That is, to create the bundles (referred to as "packing"
>  by some) the first place (before and/or after RA).
>  ...
>  The bundle constraint (the wide instruction template(s) supported by the machine)
>  can be implemented with the state machine approach or just a resource table.

We have thought about it from a VLIW perspective. Yes, you can integrate scheduling with packetization. I committed a DFA-based packetization mechanism last week and that can be used by the scheduler to make more intelligent decisions for a VLIW target. The flow that Evan described is flexible enough to accommodate both an integrated scheduler and a pre and post-scheduling packetizer. Some VLIW targets may need all three phases; others can use some combination of the three.


Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

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