[LLVMdev] RFC: Machine Instruction Bundle

Pekka Jääskeläinen pekka.jaaskelainen at tut.fi
Tue Dec 6 02:06:27 PST 2011

On 12/05/2011 11:50 PM, Jakob Stoklund Olesen wrote:
> By adding a new<internal>  flag to MachineOperand, the register allocator can
> effectively treat a bundle as a single instruction. All MachineOperands
> inside a bundle are treated as if they all belong to the single instruction.
> This even works when rewriting operands.

This sounds like a simple and good solution to the "parallel bundle" semantic
worries I had.

What about instruction scheduling? Has anyone thought how/if isched could work 
with parallel bundles? That is, to create the bundles (referred to as "packing"
by some) the first place (before and/or after RA).

I'm not familiar enough with the current LLVM isched work so I do not know
if the current algorithms could be used for static scheduling for VLIWs.
Is one really required to write a separate "packer" that just tries to pack
sequential(?) instructions to bundles without trying to reorder to improve
the packing density?

How I see it, "packing" is just instruction scheduling with an additional
"what can be in a single bundle and in what order"-scheduling constraint and has
fixed cycles (bundles) for the instructions as an outcome. The bundle
constraint (the wide instruction template(s) supported by the machine) can be
implemented with the state machine approach or just a resource table.

VLIW scheduling requires also multiplicity for the FU resource constraints.
Can those be described in the current TableGen format? Clustered (or in
general, not-fully-connected) VLIWs also require connectivity information
(which FUs are connected to which RFs) but that can be modeled with
register classes, I've been told.


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