[LLVMdev] Complex regalloc contraints

[Jakob Stoklund Olesen]

On Sep 7, 2010, at 3:01 AM, Carlos Sanchez de La Lama wrote:

> The machine I am targeting has some special requirements for some
> operations, say:
> 
> ADD or1, ir1, r5
> 
> would add ir1 (input reg 1) and r5 and put the result in or1 (output reg
> 1). The point id that input and output regs have to go paired (this
> meaning an addition of ir1 with whatever always goes to or1, or an in
> general irX + whatever goes to orX).
> 
> AFAIK, InstrInfo.td only allow "$src = $dst" type constraints. Is it
> possible to describe more complex src/dst relations, like the one I
> need?

No, that is the only type of constraint supported (besides register classes).

> This latter way is probably too hackish and that's why I am having so
> weird problems, but I have found no other way to achieve this. Is there
> one?

It sounds like you need to present a more abstract architecture to the LLVM register allocator, but it is difficult to suggest one from the description you have given.

/jakob