[LLVMdev] Complex regalloc contraints

[Carlos Sanchez de La Lama]

Hi all,

The machine I am targeting has some special requirements for some
operations, say:

ADD or1, ir1, r5

would add ir1 (input reg 1) and r5 and put the result in or1 (output reg
1). The point id that input and output regs have to go paired (this
meaning an addition of ir1 with whatever always goes to or1, or an in
general irX + whatever goes to orX).

AFAIK, InstrInfo.td only allow "$src = $dst" type constraints. Is it
possible to describe more complex src/dst relations, like the one I
need?

Also, I have tried making say or1 and ir1 parts of a single superreg
(op1reg), using "$src = $dst" and a pattern to wrap the operations with
EXTRACT_SUBREG/INSERT_SUBREG compounds. But in that case I have two
problems: 1) the LLVM op operates over a vector reg, thus *overwrites*
the input also (and that is not what our machine does) 2) LLVM needs to
be able to copy those regs for two-addr instruction rewritting, but
input regs are not readable and output regs are not writable.

This latter way is probably too hackish and that's why I am having so
weird problems, but I have found no other way to achieve this. Is there
one?

Thanks and BR,

Carlos